Systems and methods for wireless communications

ABSTRACT

The invention provides systems and methods that include, inter alia, wireless communication systems that integrate wireless receivers and transmitters with host computer platforms and that include a data access channel that delivers into the memory space of an application program digital data that is representative of a base band modulated signal. Accordingly, these systems can employ wideband digitization of an incoming signal, such as an RF signal, direct the digitized data into the application memory space of a general purpose workstation, and allow an application program operating on the general purpose work station to perform the digital signal processing that obtains the information encoded within the digitized signal.

CLAIM OF PRIORITY

[0001] This application is a continuation of U.S. application Ser. No.09/231,335, filed Jan. 13, 1999, which claims priority to U.S.Application No. 60/071,485, filed Jan. 13, 1998, both of which arehereby incorporated herein by reference.

GOVERNMENT CONTRACT

[0002] This invention was made with government support under ContractNumber DABT63-95-C-0060 awarded by the U.S. Army. The government hascertain rights in the invention.

FIELD OF THE INVENTION

[0003] The invention relates in general to communication systems and inparticular to wireless communication systems that can communicate audio,video and data signals.

BACKGROUND OF THE INVENTION

[0004] The field of wireless telecommunications has grown rapidly inrecent years, and the demand for wireless telecommunication services andequipment continues to grow. This notable growth is due, in part, to theproliferation of new communication standards and the development of newhardware technologies. For example, the successful adoption of cellulartelecommunication standards has promoted the growth of the cellulartelephone industry and driven the development of smaller and more powerefficient cellular telephones that incorporate new hardware technologiesthat provide for greater conversion rates between the analog and digitaldomain, and greater digital signal processing power.

[0005] Although the new these new standards and hardware technologieshave provided a slew of new devices that often work exceptionally well,these devices are generally dedicated to a specific application and arebased on application specific hardware designs are almost alwaysrestricted in the functionality they can provide. Specifically, the newhardware devices generally employ application specific hardwarearchitectures, including proprietary bus architectures, components, andother proprietary elements, that reduce the flexibility of these systemsand make the systems difficult to upgrade, difficult to extend, anddifficult to scale.

[0006] In part to address the extensibility issues that arise from theuse of proprietary hardware architectures, digital radios, or softwareradios, have been developed. Software radios employ analog to digitalconverters and digital signal processors to process a broadcast bandsignal and generate a stream of data that is representative of theinformation being transmitted on a selected channel. Brannon, Brad,Wide-Dynamic-Range A/D Converters Pave the Way for WidebandDigital-Radio Receivers, EDN (Nov. 1, 1996). The datastream can then bepassed to a software application that further processes the datastreamto perform the application at hand. For example, a software radioapplication that implements an FM radio receiver can process an incomingdatastream to decode the signal transmitted on a particular radiofrequency assigned to a particular radio station and can play the musicor voice signals that were encoded on that RF signal.

[0007] Software radios, therefore, provide greater flexibility byproviding a datastream to a computer system that can employ anapplication program to process the datastream as the program dictates.Accordingly, by changing the software that processes the datastream, auser can upgrade, or extend, the functionality that is being implementedby the software radio. This provides greater flexibility and thereforemore powerful telecommunication devices.

[0008] Moreover, software radios exist today that provide the datastreamof the modulated or demodulated data into an application program thatcan be run on a general purpose workstation. This use of general purposeworkstations more readily integrates wireless communication functionswith data processing functions and more easily allows wirelesscommunications to be integrated into other data processing systems. Forexample, this increased level of integration allows software radios toleverage the power of wireless communications along with the resourcesavailable on a data processing platform, such as network communications,greater data storage, and other such capabilities.

[0009] Although software radios provide increased flexibility overapplication specific hardware architectures, software radios stillemploy application specific digital hardware or digital signalprocessors (DSPs) for performing the signal processing that develops thedatastream that represents the information encoded within a broadcastsignal. Accordingly, in a software radio the signal processing happenslargely within dedicated signal processing hardware, typically on aapplication specific platform, and little to no opportunity is providedto adapt or alter the way in which signal processing takes place togenerate the datastream. For example, even in a software radio,dedicated hardware will still perform the basic signal processing thatdetermines the width of a channel, the number of channels that can beprocessed at once by the software application, and other similarparameters.

[0010] Accordingly, software radios still place a boundary of anapplication specific hardware architecture between a user's applicationsoftware and the demodulated data available from the RF signal. This inturn limits the flexibilty of the software radio and reduces the abilityto provide telecommunication functions across the data processingenvironment.

SUMMARY OF THE INVENTION

[0011] Accordingly, it is an object of the invention to provide wirelesstelecommunication devices that can adapt or alter the signal processingbeing carried out by the wireless communication device.

[0012] It is yet another object of the invention to provide wirelesscommunication systems and methods that provide greater flexibility overthe datastream generated by the wireless communication device.

[0013] Other objects of the invention will, in part, be obvious, and, inpart, be shown from the following description of the systems and methodsshown herein.

[0014] The invention provides systems and methods that include, interalia, wireless communication systems that integrate wireless receiversand transmitters with general purpose processing platforms and thatinclude a data access channel that delivers into the memory space of anapplication program digital data that is representative of a modulatedsignal. Accordingly, these systems can employ wide band digitization ofan incoming signal, such as an RF signal, direct the digitized data intothe application memory space of a general purpose processing platformand allow an application program operating on the general purposeprocessing platform to perform the digital signal processing thatobtains the information encoded within the digitized signal.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The foregoing and other objects and advantages of the inventionwill be appreciated more fully from the following further descriptionthereof, with reference to the accompanying drawings wherein;

[0016]FIG. 1 depicts a functional block diagram of a wirelesscommunication system that includes an application program for processinga modulated signal;

[0017]FIG. 2 depicts a functional block diagram of one interface cardsuch as that depicted in FIG. 1;

[0018] FIGS. 3A-3C depict in diagrammatic form the flow of data betweenthe components of the system depicted in FIG. 1;

[0019]FIG. 4 depicts as a functional block diagram one embodiment of acellular receiver process that processes digitized IF samples deliveredinto the memory space of the process;

[0020]FIG. 5 depicts an alternative embodiment of a downconvertingmodule that can be employed with the cellular receiver process depictedin FIG. 4;

[0021]FIG. 6 depicts the network layers of a network interface cardaccording to the invention; and

[0022]FIG. 7 depicts as a functional block diagram, the softwarecomponents of an application for transmitting packets of network data.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

[0023] To provide an overall understanding of the invention, certainillustrative embodiments will now be described, including a cellularreceiver wireless communication system. However, it will be understoodby one of ordinary skill in the art that the systems and methodsdescribed herein can be adapted and modified for other applications andthat additions and modifications can be made to the embodimentsdescribed herein without departing from the scope of the invention.

[0024] The systems and methods described herein include, inter alia,wireless communication systems that integrate wireless receivers andtransmitters with host computer platforms and that include a data accesschannel that delivers into the memory space of an application programdigital data that is representative of a modulated signal. Accordingly,these systems can employ wide band digitization of an incoming signal,such as an RF signal, provide the digitized data to the applicationmemory space of a general purpose processing platform and allow anapplication program operating on the general purpose workstation toperform the digital signal processing that obtains the informationencoded within the digitized signal. To this end, the systems andmethods described herein optionally include a data interface board forexchanging data between a wireless receiver/transmitter and aninput/output bus of the general purpose processing platform, as well asoptionally include a programming environment that provides libraries ofsoftware routines as well as a framework that includes a class or set ofclasses that can embody an abstract design for a solution to a wirelesscommunication application.

[0025]FIG. 1 depicts a wireless communication system 10 that includes areceiver/transmitter 12, a converter 14, a host platform 16, apersistent memory device 18, and an input/output device 20. The depictedsystem 10 provides a platform on which processes can be run to perform adesired wireless communication operation. As shown in FIG. 1, thereceiver/transmitter 12 couples through a bidirectional transmissionpath to the converter unit 14, which in turn couples through abidirectional transmission path to the host platform 16. The hostplatform 16 couples through a bidirectional transmission path to thepersistent memory device 18, and through a bidirectional transmissionpath to the input/output device 20. Simply for the purpose of describingthe systems and methods of the invention, the system 10 will describedas including an application program that implements a cellular receiverfor processing the U.S. cellular band. However, it will be understoodthat the systems described herein are in no way limited to anyparticular application, and that other application programs can be runon the system 10 for implementing other applications, including cellularmodems, radio receivers, television receivers, wireless networkinterface cards, remote control devices, such as garage door openers,and channel selection devices, or any other type of wirelesscommunication service, virtual device or application.

[0026] In one embodiment, the depicted receiver/transmitter 12 comprisesan RF receiver unit that can act as a front end for the system 10 tocollect and translate a selected broadcast band of interest to abaseband or a substantially base band signal. To this end, thereceiver/transmitter 12 depicted in FIG. 1 includes an antenna element22 that couples to a preamplifier 24, which couples to a wideband filter28. The functional components depicted within the receiver/transmitterunit 12 illustrate that the receiver can collect an RF signal andgenerate from that RF signal a wideband IF signal that can betransmitted to the converter unit 14. In one embodiment, thereceiver/transmitter unit 12 can include a commercially available RFreceiver, such as the type manufactured and sold by the Tellabs Companyof Lisle, Ill. However, it will be apparent to one of ordinary skill inthe art that other receiver/transmitters, or tuners can be employed, andthe receiver/transmitter device selected depends in part on theapplication. For example, the unit 12 depicted in FIG. 1 is described asa receiver/transmitter. However, it should be apparent that dependingupon the application the receiver/transmitter 12 can be solely areceiver unit, or alternatively solely a transmitter unit. Moreover, thesystem 10 can include a plurality of receiver/transmitter devicesthereby allowing a plurality of transmitter/receiver devices to becoupled to the host platform 16, and wherein each receiver/transmitterdevice can be capable of receiving or transmitting along differentportions of the RF spectrum, including 10 kHz to 1 Ghz, oralternatively, along portions of the microwave spectrum, infraredspectrum, visible light spectrum, or any other suitable communicationspectrum or channel.

[0027]FIG. 1 further depicts that the system 10 includes a converterelement 14. In the embodiment depicted in FIG. 1, the converter element14 is a high performance analog to digital converter of the typemanufactured and sold by the Analog Devices Corporation of Norwood,Mass. The analog to digital converter functions to convert data from theanalog domain into the digital domain, and conversely to translate databetween the digital domain and the analog domain.

[0028] The design and use of converters such as the converter 14, arewell known in the art of electrical engineering, and any suitableconverter can be employed by the system 10 for translating signalsbetween the analog domain and the digital domain. Moreover, it will beunderstood that the sampling rate at which the converter 14 is drivennormally depends on the bandwidth of interest and, typically the highestfrequency in the selected band and the amount of oversampling that isdesired for purposes of improving the signal to noise ratio in thedigital domain.

[0029] The converter element 14 couples through a bidirectional path tothe host platform 16, shown in FIG. 1. The host platform 16 can be ageneral purpose computer work station, such as for example an IBMcompatible personal computer running a Pentium class microprocessorhaving MMX capabilities and operating at a clock frequency of 200megahertz, with a 33 megahertz internal PCI bus, and at least 64megabytes of internal random access memory (RAM). The host platform 16is shown diagrammatically in FIG. 1, and includes an interface device30, the CPU 32, the operating system 34, computer memory 36 that canmaintain a memory space 38 for data and a program memory space 40 forapplication processes and an output controller 48 that couples to theoutput device 20. The host platform 16 is merely one embodiment of ageneral purpose processing platform, and it will be understood by one ofordinary skill in the art that the term general purpose platformencompasses computing platforms that are designed for providing aflexible architecture to facilitate the loading and running of differentapplication programs.

[0030] In this example, the host platform 16 operates to perform signalprocessing on the digitized wideband IF data delivered from theconverter 14. To this end, the host processor 16 can run the depictedprocess 44 within the program memory space 40. The operating system 34,which controls resources on the host platform 16, such as the memoryresource provided by the computer memory 36, can allocate to the process44 a portion 42 of the memory space 38 for use by the process 44. Aswill be described below, the operating system 34 can control the flow ofdata between the interface 30 and the portion 42 of the data memory 38that has been allocated to the process 44, and can allow high bandwidthdata transfers between the process 44 and the interface 30. The directdata transfer between the process 44 and the interface 30 provides tothe process 44 a constant stream of data samples, or blocks of datasamples to process, and reduces or eliminates the time delays andtransfer jitter than can arise from the virtual memory operations of theoperating system 34, multiple levels of caching and competition forinput/output resources.

[0031]FIG. 1 further depicts that the host platform 16 can couple to apersistent storage device 18, which can be a hard disk drive, a tapedrive, a flash memory or any other type of memory device that canprovide persistent storage of data. The system 10 can employ the storagedevice 18 for storing wideband IF data, demodulated data, or any portionof the data processed by the signal processing application programoperating on the host platform 16. FIG. 1 further depicts that the hostprocessor 16 can include an output controller 48 that couples to theinput/output device 20. In one embodiment, the output controller 48 canbe a sound card, such as the Sound Blaster® card manufactured and soldby Creative Labs of Stillwater, Okla. For this example, the sound cardcan couple to one or more audio input/output devices such as amicrophone and a pair of amplified speakers of the type commonlyemployed with commercial personal computers. In other applications, theinput/output device can include a data display for displaying datatransmitted over the wireless channel, as well as a video display suchas a television monitor. Moreover, the input/output device can alsocomprise a device, such as a remote control device, that can be employedfor generating or responding to a command signal transmitted over awireless channel.

[0032]FIG. 2 depicts one embodiment of an interface card, such as theinterface card 30 shown in FIG. 1. More particularly, FIG. 2 depicts aninterface card 60 that can be formed as a plug-in card, or a daughtercard, that can be inserted into an expansion slot on the motherboard ofthe host platform 16. As shown in FIG. 2, the interface card 60 caninclude a PCI/PCI bridge 62, a configuration memory 64, a PCI controllercomponent 68, an output page address memory 70, and input page addressmemory 72, an output data memory 74 and an input data memory 78. Theinterface card 60 depicted in FIG. 2 can connect through the PCI/PCIbridge 62 to the PCI bus of the host platform 16, and can connectthrough the output/input data memories 74 and 78 to the analog front endof the system, such as the converter 14 depicted in FIG. 1.

[0033] More specifically, the interface card 60 depicted in FIG. 2 canbe a full-size PCI card that is compliant with version 2.0 of the PCIspecification. The interface 60 acts as a bus master to perform directmemory access, off loading the transfer of data from the CPU 32, and canact as a target when accessing its control and status registers.

[0034] The PCI/PCI bridge 62 can be any commercially available PCIbridge device suitable for interfacing a PCI card to the PCI bus of awork station, such as the host platform 16. One such PCI/PCI bridgecomponent is the 21050-AA, manufactured and sold by the IntelCorporation. The PCI/PCI bridge 62 can couple via a transmission path toa PCI controller element 68. The PCI controller element 68 can be anysuitable element for controlling the actions of the interface board 62,and in one embodiment is a field programmable gate array (FPGA) such asthe type manufactured by the Xilinx Corporation of Millipatas, Calif.The FPGA can be programmed to contain the PCI controller and DMA engine,to provide a high bandwidth interface between the analog front end andthe computer memory 36. Configuration data can be stored in theconfiguration memory 64, and accessed by the controller 68 at start-upor during operation.

[0035] In an optional embodiment, the interface card 60 can have adaughter card interface to which the converter 14 can connect. Adaughter card can carry the converter 14, as well as any additionalcomponents that can be employed for generating data to be sent to theinterface card 60. The depicted interface 60 includes a pair of databuffer memories, such as FIFO memories, each of which exist in the inputand output directions for those systems that couple to both receiver andtransmitter units. Optionally, a single buffer can be provided forsystems which connect only to a receiver or a transmitter unit. Thebuffers absorb jitter that arises from the bursty access to the PCI busof the host platform 16. In the input direction, the buffer can holdincoming samples until the interface device 60 acquires the PCI bus andcan transfer the data into the memory 36 of the host computer 16. In theoutput direction, the buffer can hold excess samples that have beentransferred from memory 36 but are waiting to be accepted by theconverter 14. The buffers 74 and 78 also serve to temporally decouplethe timing of the interface card 60, which typically operates using thePCI clock, from converter 14 or from a daughter card, which typicallywould operate using the converter sampling clock. This reduces, oreliminates, the need for designs that must take into considerationsynchronization or metastability issues. It also separates the datatransfer and processing from the fixed rate realm of the analog frontend, allowing it to be bursty, or sporadic, as is common with shareddata transfer resources.

[0036] The PCI interface between the interface card 60 and the PCI bus,in the depicted embodiment, has a capacity of about one Gbit/sec. Thereare also specified upgrade paths for increasing the PCI bus bandwidth bydoubling the width from 32 to 64 bits and doubling the speed from 33megahertz to 66 megahertz, enabling greater bandwidth. Although theinterface card 60 depicted in FIG. 2 contemplates interfacing to a PCIbus, it will be understood by one of ordinary skill in the art that inother embodiments, an interface to an ISA bus, an S-bus, or any otherdata bus capable of transferring information from an interface card tothe host workstation 16 can be practiced with the systems describedherein.

[0037] The depicted interface card 60 acts as a PCI bus master andinitiates transfers on the PCI bus. Accordingly, the interface card 60can perform DMA sample streams to or from the computer memory 36 at ahigh speed with minimal intervention from the CPU 32. In one embodiment,the interface card 60 implements a variant of scatter/gather DMA thatstreams pages of data between the computer memory 36 and the interfacecard 60. To that end, the interface card 60 includes two page addressmemories, 70 and 72, which can be FIFO memories, one being assigned forinput and one being assigned for output. The memories can hold physicalpage addresses associated with buffers in a memory space, such as thevirtual memory space that is organized by the operating system 34. Forexample, at the end of a page transfer, the interface 60 can read thenext page address from the head of the appropriate page address memoryand begin to transfer data to or from the memory 36. The interface card60 can trigger an interrupt when the supply of page addresses runs low,and the page addresses can be replenished by the interrupt handler inthe device driver associated with the interface card 60. Accordingly,the interface card 60 stores physical page addresses within the memories70 and 72, directly on board the interface card 60. Optionally, the pageaddresses could be stored in a memory table maintained within thecomputer program memory 36. The interface card 60 depicted in FIG. 2 cantransfer complete pages of data between the computer memory 36 and theinterface card 60. The transfer of complete pages is understood toresult in page aligned, integral page length buffers that are more easyfor the operating system 34 to manipulate.

[0038] The interface card 60 operates in cooperation with the operatingsystem 34 to achieve the direct memory access transfer of a data bufferinto the application data memory 38. In one embodiment, the operatingsystem 34 can be an implementation of the Unix operating system thatprovides a multitasking operating system that includes a virtual memorysystem for controlling memory resources on the platform 16. In onespecific embodiment, the operating system 34 is the Linux operatingsystem that provides a Unix-like operating system for the Intelprocessor architecture. Other versions of Unix, or other operatingsystems can be employed without departing from the scope of theinvention. Continuing with the example of a Unix operating system, theoperating system can be modified to include a device driver and anenhanced virtual memory system, each of which operate to achieve thedirect memory data transfers of pages of data. The device driver allowsfor continuous data transfer between the interface card 60 and theapplication data memory 38. To this end, the system can employ a ring ofbuffers into which samples can be transferred. These buffers can be partof the operating system kernel virtual memory space, and can be lockeddown in physical memory. Portions of the memory can be locked down usingany suitable technique, including the m_lock system call. The devicedriver can initially fill the input page address memory 72 withaddresses from buffers at the head of the ring of buffers. When thismemory 72 empties to a certain, programmable, level, the interface card60 generates an interrupt, and the interrupt handler transfers morebuffers from the head of the ring. The level that can trigger theinterrupt can be set such that there are sufficient pages remaining toabsorb samples arriving before the interrupt handler can provide newaddresses.

[0039] FIGS. 3A-C depict schematically the flow of data that occurs asthe data travels through the receiver/transmitter 12, into the ring ofbuffers and then onto the application memory 38. Specifically, FIG. 3Adepicts that an RF data transmission can be picked up by a receiverunit, such as the receiver/transmitter 12 depicted in FIG. 1. In FIG.3A, the receiver comprises a multi-band front end that can be softwarecontrolled to select a center frequency and a width of an RF band. Forexample, the 95X family of wideband receivers manufactured by theRockwell Company provide multi-band front ends that can be configuredthrough software to select a center frequency and a width of an RF bandin the range spanning between 2 MHz to 2 GHz. Such front ends allow formulti-band, multi-mode radio systems. In another example, the front endcan operate in the 2.5 GHz ISM band. As further shown by FIG. 3A, thewideband signal from the receiver/transmitter 12 can be passed to aconverter, such as the converter 14, that can perform direct sampling,band pass sampling, or any other suitable sampling process to provide astream of digitized IF data. In one embodiment, the IF signal can bedigitized by a 12 bit converter such as the AD9042 convertermanufactured by the Analog Devices Company. This converter is capable ofdigitizing signals at a rate of 40 MSPS. This provides a 20 MHz IFbandwidth. As shown in FIG. 3A, the stream of digitized IF data can beprovided to an interface with the host computer, such as the depictedPCI interface 30.

[0040] The PCI interface can perform a data transfer into the memory 34of the host platform 16 at a transfer rate that is sufficiently high tomeet the timing demands of the process that is performing signalprocessing on the data, such as the process 44. For example, to transfera stream of 16 bit samples of a 10 MHz wide IF band (i.e., a minimum 20MHz sampling rate) to the application process, a 320 Mbits/sec data rateis required. FIG. 3A depicts this transfer of data into the memory 34,by showing the transfer of pages of digitized IF data into a ring buffer50 that is maintained within the virtual memory space of the kernel. InFIG. 3A, the ring buffer 50 includes four buffers, 52, 54, 56 and 58,each of which as a plurality of pages capable of storing data. However,it will be apparent to one of ordinary skill in the art that the numberof buffers provided by the ring buffer 50 can depend upon theapplication and each buffer can optionally include hundreds of pages ofmemory space. As discussed above, the interface card 30 has a list ofpage addresses that designate the memory locations into which theinterface card 30 is to provide data. As the interface card operates,pages of data are transferred into the buffers of the ring buffer 50,and the ring buffer 50 can begin to fill. Accordingly, the ring buffer50 stores data to be transferred to the application memory 38, andoptionally provides sufficient storage of data to accommodate thosetimes when the application program is not able to process data at therate at which data is being delivered, thereby allowing the applicationcan catch-up by, from time to time processing the buffer faster than itfills.

[0041] To transfer data to the application memory space 38, the enhancedvirtual memory system can act to swap buffers from the application'svirtual memory space with buffers in the kernel's virtual memory space.For example, when an application makes a request to read data from thedevice driver, the application program can be transferred the buffer atthe tail of the buffer ring 50. To deliver this buffer at the tail ofthe ring 50 across the kernel-application boundary, the system 10performs a buffer swap operation. FIGS. 3B and 3C depict the transfer ofdata from the kernel virtual memory space to the memory space of theapplication program.

[0042] Specifically, FIGS. 3B and 3C depict the kernel virtual memoryspace and the buffer ring 50 maintained therein, as well as theapplication memory space with a buffer 66 stored therein. Each of thebuffers depicted in FIGS. 3B and 3C provide storage for a certain amountof data. Associated with this storage are both virtual addresses,depicted on the left-hand side of the buffer 58 as numbers 0-5, andphysical addresses, depicted on the right-hand side of the buffer 58 bythe numbers 6, 3, 58, 467, 2 and 94. As will be apparent to one ofordinary skill in the art, a physical memory address is representativeof the actual physical memory location within the computer memory 34that is storing the data. Similarly, in the application memory space thebuffer 66 has a plurality of pages with these pages having associatedvirtual memory addresses and physical memory addresses. For buffer 66the virtual memory addresses are depicted by numbers 0-5, and thephysical memory addresses are depicted by numbers 2, 5, 98, 105, 3 and6. To achieve the transfer of data between the kernel virtual memoryspace and the memory space of the application program, the physicalmemory of the buffer being transferred from the kernel virtual memoryspace is swapped out from underneath the virtual address of the buffer66 in the application memory space, thereby swapping the buffer providedby the process 44 for the buffer in the system kernel. In one practice,each page in the user buffer is faulted into a distinct physical page.The physical addresses in the page table entries for the kernel and userbuffers are then swapped, and therefore, the system affects a datatransfer into the application data space by altering the page tablewithin the virtual memory system. The manipulation of Page tablesfollows from principles well known in the art, including principles setforth in Bach, Maurice, J, The Design of the Unix Operating System,Prentice-Hall, Inc. (1986). Moreover, it will be apparent to one ofordinary skill, that any system for swapping a buffer from the kernelmemory space with a buffer in the application memory space can bepracticed with the system described herein.

[0043] To facilitate the swapping of buffers, the application program,such as the process 44 can, upon initialization, identify or define thesize and number of buffers in the buffer ring 50, therefore allowing theprocess 44 to be aware of the size of the buffer to be provided to anyREAD system calls made by the operating system. Accordingly, once theapplication program performs a malloc( ) system call, a memoryallocation will occur that allocates a memory space that is coordinatedwith the size of a buffer in the buffer ring 50. Consequently, thebuffers swapped between the kernel memory space and the applicationmemory space are the same size.

[0044] When outputting data, the process 44 can write to the interfacecard 60, treating the card 60 as an I/O device. Optionally, the devicedriver can maintain a queue of buffers that the process 44 has writtento the device driver. The size of the queue can be bounded to keepprocesses in applications from employing all of the physical memoryavailable on the host platform 16. In operation, the device driver canfirst store within the output page address FIFO 70 with addresses ofbuffers at the head of the queue. When the output page address FIFO 70empties, or empties to a certain, optionally programmable, level, aninterrupt can be triggered by the interface 60 and the interrupt handlerof the operating system can replenish the FIFO memory 70 from buffers atthe head of the queue, if they are available.

[0045] In one embodiment, a system as described herein and running on a200 MHz pentium pro platform running Linux with a 33 MHz, 32 bit-widePCI bus, the IO system has been shown to support continuous samplestream rates at up to 512 Mbits per second. The peak burst rates are 933Mbits per second for input and 790 Mbits per second for output.

[0046] Returning to FIG. 1, it can be seen that with the digitized IFdata in the program memory 36, the process 44 can then perform signalprocessing on the digitized IF samples to demodulate the transmittedsignal. In one embodiment, the process 44 comprises a cellular receiverprocess that demodulates the wideband digitized IF data to provide awideband digital receiver capable of operating in the “A-side” of theU.S. cellular band. This cellular receiver process provides a receiverthat can continuously monitor 10 MHz of the cellular band and providethe capability to demodulate FM signals anywhere in that band. In thisembodiment, the receiver/transmitter 12 and converter 14 can beintegrated into a single unit that comprises a Tellabs RF receiver thattranslates the 825-835 MHz band to a baseband signal and then samplesthe signal at 25.6 MSPS. The 12-bit sample stream is fed to theinterface card 30 which performs direct memory access to deliver thesamples into the memory 36 of the host 16 for processing by the process44. The process 44 can control the system parameters, such as channelfilter size and the various sample rates. This allows parameters to bemodified even while the receiver is operating.

[0047]FIG. 4 provides a function block diagram of one cellular receiverprocess that can demodulate the sampled IF data being provided to theprogram memory 36. The cellular receiver process can be an executingcomputer program that operates in the program space 40 of the computermemory 36. The computer program can be written in C, C++, Java, or inany suitable computer language, and developed using standard softwaredebugging tools. The program can also include routines from commerciallyavailable components, such as the FFTW package developed by Matteo Frigoand Steven G. Johnson, and freely distributed, which provides routinesof signal processing algorithms. Other commercially available librariesof routines or sets of classes for building user interfaces, or forother functionality can be employed. As is known to those of ordinaryskill in the art, the program can comprise a plurality of routines,classes or modules, each of which perform a portion of the processingthat is carried out by the cellular receiver process 80. As depicted inFIG. 4, the cellular receiver process 80 can include a channel selectionstage 82, a quadrature demodulator stage 84, a low pass filter anddecimation stage 88 and an audio band pass filter 90 and an outputcontroller 48. As discussed above, the IF samples can be providedthrough DMA transfer into the memory space of the application program.The IF samples can be transferred at the system transfer rate, and thecellular receiver 80 can be responsible for operating at sufficientspeed to process incoming samples, thereby avoiding the dropping ofsamples.

[0048] As depicted by FIG. 4, the cellular receiver process 80 canemploy a “data pull” architecture. While the flow of data is from inputto output, the flow of control is from output to input. By placingcontrol downstream, the architecture facilitates the construction ofsystems that can aggressively employ lazy evaluation and adapt to therequirements of the downstream modules. The total amount of processingthat needs to be done is reduced because downstream components canrequest just the data they need from upstream modules. Consider, forexample, an audio system to which a variety of output devices can beattached. The driver for the output controller 48 can control the amountof data required depending upon the application, for example telephonequality, at 8 kHz sampling rate with 8 bit quantization, or CD qualityaudio, at 44 Khz sampling rate with 16 bit quantization.

[0049] The depicted cellular receiver process 80 employs an upstreamcommunication path for controlling data transfer between the stages ofthe process. In one practice, each module is capable of requesting datafrom the next upstream module. Accordingly, each module can call theimmediately upstream module (or modules) requesting the needed data. Thedata delivered between modules can be done on a sample by sample basis.Alternatively, the process 80 can operate on blocks of data, orpayloads. The data payloads, such as the depicted payloads 92, 94 and 98can be made large enough to take advantage of data and instructioncaching effects, but small enough to avoid introducing unacceptablelatency. To process the data payloads, the signal processingapplications can employ algorithms designed to work on blocks of datarather than on single samples, which for example would include signalprocessing algorithms such as the fast Fourier transform. Thedevelopment of other such algorithms follows from principles well knownin the art, including principles set forth in Oppenheim et al, DigitalSignal Processing, Prentice-Hall, Inc. (1975).

[0050] To process the data, the cellular receiver process 80 includesthe channel selection filter stage 83. This stage, or module, has thetask of extracting from the digitized IF samples a narrowband FM signal(AMPS channel bandwidth is 30 kHz) from a 10 MHz wide frequency band.This depicted stage 83 accomplishes this task using a filter design thatcombines three steps of translating the signal to baseband, lowpassfiltering and decimating to an intermediate sample rate. This step ofprocessing comprises the largest portion of the computational load. Thechannel selection filter 82 employs the raw samples from the RF frontendat R_(S)=25.6 MSPS as input and produces a complex baseband signal at avariable intermediate sample rate, R_(D).

[0051] Separating narrowband channels in a wideband receiver is acomputationally intensive task that is usually done using specialpurpose hardware, such as a digital down-converter (DDC) implemented indedicated hardware. Rupert Baines, the DSP Bottleneck, IEEECommunications Magazine, 33(5): 46-54 (May 1995). The wideband signal istranslated to a complex baseband signal by the quadrature multiplier andthen lowpass filtered to prevent aliasing due to decimation. Specialpurpose FIR filters for decimation exist that do this operationefficiently—which is important since the sample rates for a widebandreceiver could be in excess of 30 MSPS. Estimates have been made that achannel selection filter can require about 100 operations per inputsample for a total of 3000 MOPS.

[0052] In one embodiment, the channel selection filter 82 follows thestructure of a hardware DDC. Multiple threads could be employed toimplement in software the structure of the hardware DDCS, wherein theseparate steps of the down-conversion process, that is, the generationof the sine/cosine multiplication factors, frequency translation, andfiltering, are done in separate physical locations in the DDC, and ahigh degree of pipeline parallelism is achieved. Furthermore, there canbe additional fine grained parallelism within the FIR filter.

[0053]FIG. 5 depicts an alternative embodiment of a software DDC, thatoperates to perform reduced processing of samples at the high samplerate and reduce the rate early in the processing chain. As shown in FIG.5, the software DDC intakes samples of the digitized wideband IF signaland provides the samples to two routines, represented functionally byblocks 102 and 104, for performing frequency translation and decimatinglow pass filtering, to produce in phase and quadrature signals. Both thein phase and quadrature signals are provided to the logic block 106.Logic block 106 can collect the data and provide any formatting andtransfer functions required for delivering the data payload to anothermodule. In this embodiment, an FIR filter is employed (versus alower-order IIR filter) to allow the production of an output signal thatdepends upon the filter input samples, x[n], and therefore to computeonly those output samples, y[n], that will be required after decimation.This is understood to reduce the computation load by taking advantage ofthe large decimation factors that will exist when processing anarrowband signal in a wideband receiver. Furthermore, the precomputedfrequency shift factors can be incorporated into a composite FIR filterand will then require only a phase correction after each output sampleis calculated. This feature makes this a time-varying FIR filter, butall of the variation can be combined into a single, time-varyingmultiplicative factor which is applied after the filtering.

[0054] In a particular embodiment, the steps of multiplication andconvolution that perform the frequency shift and filtering have beencombined to produce the composite filter. To this end, the processperforms a first step in the selection of a specific channel thattranslates (in frequency) the real-valued received signal samples, r[n],to baseband by multiplication with the appropriate complex exponential:

x[n]=r[n]e ^(−j2πfcnTs) =r[n]{ cos(2πf _(c) nTs)−j sin(2πf _(c)nTs)}  (1)

[0055] where f_(c) is the carrier frequency before translation tobaseband and Ts is the sample interval. Next, the result is filteredwith an order-M FIR filter h[m]: $\begin{matrix}{{y\lbrack n\rbrack} = {{\sum\limits_{m = 0}^{M}{{h\lbrack m\rbrack} \times \left\lbrack {n - m} \right\rbrack}} = {\sum\limits_{m = 0}^{M}{{h\lbrack m\rbrack}{r\left\lbrack {n - m} \right\rbrack}^{{- j}\quad 2\quad \pi \quad {{fc}{({n - m})}}{Ts}}}}}} & (2)\end{matrix}$

[0056] At this point, the two steps of frequency translation andfiltering can be combined: $\begin{matrix}\begin{matrix}{{y\lbrack n\rbrack} = {^{{- j}\quad 2\quad \pi \quad {fcnTs}}{\sum\limits_{m = 0}^{M}{{h\lbrack m\rbrack}{r\left\lbrack {n - m} \right\rbrack}^{{- j}\quad 2\quad \pi \quad {fcms}}}}}} \\{= {^{{- j}\quad 2\quad \pi \quad {fcnTs}}{\sum\limits_{m = 0}^{M}{\text{:}\quad {c\lbrack m\rbrack}{r\left\lbrack {n - m} \right\rbrack}}}}}\end{matrix} & (3)\end{matrix}$

[0057] where c[m]=h[m]e^(−j2πfcmTs) are the composite filtercoefficients. This process is understood to reduce the number ofcomputations, as well as eliminate the need to compute the unfilteredbaseband signal, x[n], which includes the burden of writing theintermediate results to memory only to recall them in the next step.Also, while many techniques are available to design real-valued FIRfilters to meet desired specifications with minimum order, the use ofcomplex-valued filter coefficients for h[m] is understood to impose noadditional computational cost. Accordingly, the process can takeadvantage of recent advances in the design of complex-coefficient FIRfilters to reduce the required filter order M of the original LPF,relative to a real-valued h[m], without increasing the requiredcomputation load for the final composite filter.

[0058] This above described process is only one process capable ofdownconverting the incoming signal, and other techniques that, dependingupon the application, may be less complicated to set-up and may employless memory to store filter coefficients, can be employed. The abovedescribed process also requires knowledge of the desired carrierfrequency to compute the filter coefficients, c[m], and to recompute thecoefficients when a change in the frequency to which the filter is tuned(or else precompute and store separate filters for any desiredfrequencies) is desired. However, as each set of filter coefficients maybe employed many thousands or millions of times, the cost ofprecomputing or recomputing can yield improved efficiency. Thistechnique is similar to the idea of using an analytic filter to selectonly the positive frequency components of the real-valued signal for thepassband of interest and decimating, but the combination of translationand lowpass filtering in FIG. 5 allows the filter to be quicklyredesigned to select a different f_(c). Moreover, the overhead incurredby storing these coefficients is minimal given that processing occurs ona general purpose processing platform, and that data structures areavailable as options/means for storing data. Other filter designs caninclude employ randomized algorithms as an efficient way to preventaliasing during the decimation process. Additionally, it will beapparent from the above description, that the wideband processingsystems dscribed herein can be employed to process multiple channelswithin the wideband signal, wherein each channel can be processed by aseparated process or module, or by a single process that seekstransmissions that are 8. Moreover, the system can be employed toperform channel selection according to any method including FDMA, TDMA,CDMA or spread spectrum.

[0059] Turning again to FIG. 4, in a complex FM signal, the desiredinformation (the voice, in the case of a cellular telephone) is carriedby the instantaneous frequency, which is the time derivative of thephase of the complex signal. This signal is therefore demodulated usinga simple quadrature demodulation algorithm that approximates thederivative of the signal phase by the phase difference betweensuccessive samples, appropriately scaled. This quadrature demodulationis carried out by stage 84 of the process 80.

[0060] The two final steps of processing are implemented as finiteimpulse response (FIR) filters. The first can be simply a lowpassdecimating filter that removes high frequency components that wouldcause aliasing when the sample rate is reduced to the audio rate, R_(A),typically 8K samples/sec. This is carried out in stage 88. The finalstep, carried out in stage 90, is an optional bandpass filter thatremoves out-of-band noise from the voice signal.

[0061] To facilitate the development of signal processing programs, suchas the above described cellular receiver process 80, the systemoptionally can include a programming environment that supports thedevelopment of application programs that process the digitized IFsamples to provide, for example, portable, adaptive signal processingsystems with real-time constraints. The programming environment caninclude a library of routines, or a class or set of classes, written ina computer programming language, such as the C, C++ or Java language.Optionally, the programming environment can include an object-orientedapplication framework that consists of a library of classes that aredesigned to be extended and subclassed by the application programmer,packaged along with several illustrative sample applications that usethose classes and which are designed to be modified by the applicationprogrammer. The sample applications generally constitute a system thatis useful in its own right. Frameworks can provide functionality and“wired-in” interconnections between the object classes that provide aninfrastructure for the application developer. The inter-connections canprovide the architectural model and design for developers and free themto apply their effort on the problem domain. By providing aninfrastructure, the framework can decrease the amount of standard codethat the developer has to program, test, and debug. In general, thebasic concept of a framework is well known to one skilled in the art.Some example frameworks include X Toolkit, Motif Toolkit, SmalltalkModel-View-Controller GUI, and MacApp.

[0062] Optionally, the programming environment can support adaptivesignal processing, including adaptive programming for achievingadaptation to environment factors, such as for example, an applicationprogram that implements a modem capable of equalizing for the channel.To this end, the system can provide algorithms to detect environmentchanges, such as channel estimation algorithms, and a mechanism forspecifying system modifications based on the detected changes.Similarly, the programming environment can support adaption to the userto allow for user requirements that may change dynamically andnecessitate changes in the system, or in operating parameters of thesystem. For example, the programming environment can provide for userchanges such as a user changing a parameter representative of thestation on a radio. Similarly, the programming environment can allow foractivating a control representative of a push button for selectingbetween AM/FM broadcasts. The change between AM and FM broadcastsrequires a change in algorithms employed by the application program todemodulate the digitized IF data. The programming environment canfurther include routines or classes for allowing functional adaptation.Functional adaption provides for signal processing techniques, such as aphase-locked loop, that are inherently adaptive. These techniquestypically adapt to the signal, and may modify system parameters orfunctionality to meet specified requirements. For example, a receiverattempting to lock on to the start frequency of a hopping sequence canadapt the system to examine different frequencies until a start code isfound. This type of adaptation can be driven by a specified constraint,without the need for an external change, or in cooperation with anexternal change. Additionally, the system can provide for adaption inresponse to the availability of resources. For example, the applicationprogram can detect if there are spare CPU cycles available. If CPUprocessing power is determined to be available under the current systemconditions, then running a more computationally intensive channelestimation algorithm can be employed to seek better overall systemperformance. Conversely, if the resources suddenly become scarce due toa burst of activity by other processes, the system can adapt, perhaps byrunning less demanding algorithms and sacrificing some robustness oraccuracy. This form of adaptability also enables applications totransparently improve performance as faster processors become available.

[0063] The system described above, allows for the transmission andreception of cellular communications using the US cellular band.However, an advantage of performing processing in software is that thetransmission process can be separated from the reception process, andtherefore, the systems and methods described herein allow for virtualcommunication patch systems, wherein the same device can receive anddecode transmission under one protocol, and broadcast transmission underanother protocol. This allows for forming a patch between disparatewireless systems. In another example, a radio transmission broadcastusing frequency modulation, could be received and decoded, and thenencoded using amplitude modulation and rebroadcast, thereby allowing AMreceivers to receive the same data as FM receivers.

[0064] In another embodiment, the systems described herein can includenetwork interface cards (NICS) that implement signal processing insoftware, thereby providing a wireless network interface functionalitythat can be dynamically modified. The software wireless networkinterface can be compatible with a commercial frequency hopping radiooperating in the 2.4 GHz ISM band employing FSK modulation. Parameterssuch as the FSK frequency deviation and the spacing of the hoppingchannels can be dynamically modified in software, with the constraintsimposed by the hardware being the width of the IF band and the RF bandto which the signal is converted. The ability to dynamically modify thechannel width, channel spacing and the hopping sequence allows thesystem to adapt to its environment and provide better noise rejectionand immunity from hostile jamming attacks.

[0065] The software network interface architecture can be a refinementof the OSI layering model, which subdivides the existing Link andPhysical layers as shown in FIG. 6. As shown, the software NIC canconnect to a hardware device that implements the processing of layer102, the frequency conversion, and layer 104, conversion between theanalog domain and the digital domain. Once data is in the digitaldomain, the software NIC can implement those other layers that are to beperformed for network data transfers. As shown in FIG. 6, these layersinclude the multiple access layer 108, the modulation layer 110 and theline coding layer 112. The multiple access layer 108 can be implementedaccording to perform suitable protocol that shares the data transfermedium. In layer 110, the modulation of the selected IF data can occurto collect the data transmitted over the wireless channel. In layer 112,the data can be coded as required for transmission. The data link layers116 and 114 can also be implemented by any suitable technique that canperform the data encapsulation and decapsulation and thetransmit/receive media-access management.

[0066] The sequence of processing modules for the transmissionapplication is shown in FIG. 7. The system interfaces with the host atthe IP layer, through a device driver 126 that can appear to the kernelas just another network device driver. However, instead of handing thepackets off to a hardware device, this driver hands them up to userspace 122, where the software radio processing is performed. The firstlevel of processing is the network framing. For this example, thepackets can be framed and byte stuffed to carry the data. A length code,indicating the total length of the packet including the stuffed values,can be inserted after the start code. The next module takes the sequenceof bits output by the network framing layer and performs byte framing,inserting start, stop and parity bits.

[0067] The conversion of each bit into a discrete signal is performed bythe FSK module 132 and the frequency hopping module 134 then assignsthis waveform to the appropriate frequency. All of the possibletransmission waveforms can be known a priori. There are two possiblewaveforms, corresponding to 1 or 0, for each hop frequency. All of thesewaveforms can be pre-computed and stored at startup, significantlyreducing the computation required to produce the transmitted waveform.On a 180 MHz Pentium Pro 2.2 microseconds were required for producingthe IF waveform corresponding to a single bit. This corresponds to apossible transmit data rate of ≈450 kbps.

[0068] To generate continuous phase waveforms the pre-computed waveformsare actually oversampled, and a sub-sampled set, corresponding to theoutput sampling rate, are copies into the output buffer. Theoversampling allows for indexing into the buffer to match the phase, andthe pattern can be treated as a circular buffer, allowing the generationof waveforms for any bit period. After copying the samples to the outputbuffer, the phase value is updated and used as the index for thewaveform corresponding to the next bit. In a similar manner, the systemcan maintain continuous phase between hops, even when the hop occurs inthe middle of the bit.

[0069] Reception is essentially the reverse of the transmission systemshown in FIG. 7. The receiver detects the presence of a validtransmission and synchronizes to it, as well as performs the inversefunction of each of the transmission layers. Again, combining theparameters of the frequency hopping and the FSK demodulation, the systemcan constrain the receiver to look for one of the two valid waveforms ata given hop frequency. Separate functions were implemented to track thehopping sequences, and to lock onto and demodulate the bits. These bitsare de-framed, and then the IP packets is extracted. The driver thenhands the packet off to the host IP layer for processing.

[0070] Those skilled in the art will know or be able to ascertain usingno more than routine experimentation, many equivalents to theembodiments and practices described herein. For example, it will beunderstood that the systems and methods described herein can be employedfor developing baseband communication systems, as well as system fordeveloping baseband applications. It will also be understood that thesystems described herein provide advantages over the prior art includingthe ability to select one or more channels from a wideband IF signal,and selectively process the channel.

[0071] Accordingly, it will be understood that the invention is not tobe limited to the embodiments disclosed herein, but is to be understoodfrom the following claims, which are to be interpreted as broadly asallowed under the law.

We claim:
 1. A method of processing radio signals, comprising convertingbetween a wideband signal and a high sampling rate digital signal, undercontrol of a direct memory access controller in communication with aprocessor, storing samples of the high sampling rate digital signaldirectly into an application memory space without interrupting theprocessor, said application memory space being accessible by a computerprogram; processing the high sampling rate digital signal samples undercontrol of the computer program.
 2. The method of claim 1, whereinsampling is continuous.
 3. The method of claim 1, wherein samples arestored at a rate equal to the sampling rate.
 4. The method of claim 1,wherein the wideband signal has a bandwidth of 10 MHZ and sampling rateis at least 20 mega-samples per second.
 5. The method of claim 1,wherein processing further comprises modulating a signal to thedigitized IF signal.
 6. The method of claim 1, wherein processingfurther comprises demodulating a signal from the digitized IF signal. 7.The method of claim 1, wherein processing further comprises channelselection.
 8. The method of claim 1, wherein storing samples undercontrol of the direct memory access controller comprises: maintaining,in the direct memory access controller, a list of physical pageaddresses associated with buffers in memory; reading a page address fromthe list, transferring, between an input/output device and memory towhich the page address is associated, the high sampling rate digitalsignal samples; and repeating continuously the above reading andtransferring steps.
 9. The method of claim 8, wherein storing samplesunder control of the direct memory access controller further comprises:removing the page address from the list; and providing new pageaddresses by interrupting the processor when the number of pageaddresses in the list falls below a predetermined threshold, such thatan interrupt handler provides the new page addresses.
 10. A method forprocessing a radio signal, comprising: converting, in an analog domain,between a radio frequency signal and an analog intermediate frequencysignal; converting between the analog intermediate frequency signal andcorresponding digitized intermediate frequency signal data; bufferingthe digitized intermediate frequency signal data in a buffer; undercontrol of a direct memory access controller in communication with aprocessor, transferring, in page multiples, pages of digitized IF signaldata between the buffer and memory without interrupting the processor;and processing the digitized intermediate frequency signal data in acomputer program.